Instantiate primitive DFF with an an inverted clock input

The architecture is generally a global clock tree that fans out to every register in the device, and within each lab that clock tree can be inverted. THis is all handled by synthesis, i.e. if you only do one inversion of the net, synthesis will pass that down to the LAB level. If you do a bunch of inversions on each register, synthesis will figure out if they can be joined or not. Clock inversions are taken care of for you physically and you only have to deal with them logically.

As for the circuit, I don't like it since it will skew your clock. I would either use the altclkctrl block and drive the enable of it, or infer a clock enable in all the downstream logic. Either one will work.