Instantiate primitive DFF with an an inverted clock input

If doing a schematic, I either:

-throw down a FF with an inverter before the clock

- take the clock and drive it through an inverter and name the net, then just use that net to drive the FF clock(this is cleaner if a lot of signals are getting the inversion, where the first one is better if it's only a small number, as it clearly shows the inversion)

Note that both methods have the inverter get absorbed into the LAB clock inversion and there is no clock skew and no timing issues.

Now, the schematic you attached will have a skew issue to the second FF, since your clock goes through an AND gate(and because your clock is cascaded from another FF). So I would avoid that.