Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them works, but the other not. I know this sounds like there is a flaw in the design, but I checked and double checked everything. All the signals are registered... Also TimeQuest doesn't report any errors. After compilation of the design I checked the resource section in the fitter report, and found out that the number of resources used is slightly different. Although it doesn't supprise me this might be a problem. So I tryed to prevent Quartus from optimizing the netlist, duplicate logic etc. and create LogicLock regions for the two transmitter. But this caused Quartus 9.1 SP1 to stop with an internal error in the fitter :mad:. Does anybody have any suggestions how to instanciate the design twice so that the results will be the same?

--- Quote Start --- Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them works, but the other not. I know this sounds like there is a flaw in the design, but I checked and double checked everything. All the signals are registered... Also TimeQuest doesn't report any errors. After compilation of the design I checked the resource section in the fitter report, and found out that the number of resources used is slightly different. Although it doesn't supprise me this might be a problem. So I tryed to prevent Quartus from optimizing the netlist, duplicate logic etc. and create LogicLock regions for the two transmitter. But this caused Quartus 9.1 SP1 to stop with an internal error in the fitter :mad:. Does anybody have any suggestions how to instanciate the design twice so that the results will be the same? --- Quote End --- Hi, can you post the level where you instanciate the transmiiter. Only to be sure .... Do you fully constraint your design ? Clocks, I/O, .... Kind regards GPK

Hi GPK, thanks for your fast response! I attached the entity where I instanciate the IFFT, cyclic prefix etc. the top level entity of the design, and also the SDC File for the timing constraints. kind regards Christoph https://www.alteraforum.com/forum/attachment.php?attachmentid=2797

--- Quote Start --- Hi GPK, thanks for your fast response! I attached the entity where I instanciate the IFFT, cyclic prefix etc. the top level entity of the design, and also the SDC File for the timing constraints. kind regards Christoph https://www.alteraforum.com/forum/attachment.php?attachmentid=2797 --- Quote End --- Hi, nothing strange found so far. Can you describe the misbehaviour a little bit more ? Kind regards GPK

ok, let me try... I test my transmitters by activating only one subcarrier so I expect to see a single sinusodial wave on the DAC outputs, but one of the outputs (it's not always the same) oscillates in a more less random looking way. The setup and hold times at the DAC are not violated because I use a seperate clock for every channel of the DAC (delays are different on the board), and I can adjust the clock phase during runtime so that the data are sampled correctly. It appears to be that there is some sort of metastability problem? There are several different clock domains in the design, but I think I handle the transistions from one clock domain to another correctly (use synchronizers, reset sequencer), and TimeQuest doesn't report any errors which it should if there is a timing violation (if my timing constraints are correct) thanks for your help, because I'm really desperate. Christoph

--- Quote Start --- ok, let me try... I test my transmitters by activating only one subcarrier so I expect to see a single sinusodial wave on the DAC outputs, but one of the outputs (it's not always the same) oscillates in a more less random looking way. The setup and hold times at the DAC are not violated because I use a seperate clock for every channel of the DAC (delays are different on the board), and I can adjust the clock phase during runtime so that the data are sampled correctly. It appears to be that there is some sort of metastability problem? There are several different clock domains in the design, but I think I handle the transistions from one clock domain to another correctly (use synchronizers, reset sequencer), and TimeQuest doesn't report any errors which it should if there is a timing violation (if my timing constraints are correct) thanks for your help, because I'm really desperate. Christoph --- Quote End --- Hi, is it random which of the outputs is working ? Is it changing after a new P&R or after reset of the design ....? Kind regards GPK

instaciating the same architecture twice gives different results

14 Replies

Altera_Forum
Honored Contributor
15 years ago
The powerup don't care defaults to ON in quartus, set it to OFF. => settings => analysis and synthesis => more settings...

With regard to signaltap, it is true it adds further strain on timing but you can use it to exclude DAC differences.

The reset sequencer can be made variable on the two instants until both work.
also make sure all important signals are reset to known values.
Altera_Forum
Honored Contributor
15 years ago
Hi kaz,

I will set the "power up don't care" option to OFF as soon as the current compilation has finished. But a proper design shouldn't depend on this? At least in my register processes I always use the async. reset to set them to a known value, but of course I might have forgotten one, and I also don't know for sure if the used IP cores clear all the registers at power up.
Do you think that the reset is the most likely source of error in this case, or are there other pitfalls I might not be aware of?

kind regards
Christoph
Altera_Forum
Honored Contributor
15 years ago
Two instants of same design may differ because of:

(1) different input (make sure all inputs are exactly same. as a test pass same input copy to both).

(2) different output interpretation, e.g. embedded analyser results or DAC paths

(3) timing

(4) power up reset values

(5) user error

(6) fitting error

(7) flaky design

With signaltap you can compare the output at every stage readily
Altera_Forum
Honored Contributor
15 years ago
I'm really sorry I can't be more precise about the problem, but at least I think I'm now aware of all the possible pitfalls...

thanks for your help!
Christoph

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instaciating the same architecture twice gives different results

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