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Altera_Forum
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15 years ago

instaciating the same architecture twice gives different results

Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them w...
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Altera_Forum
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15 years ago

Hi kaz,

I will set the "power up don't care" option to OFF as soon as the current compilation has finished. But a proper design shouldn't depend on this? At least in my register processes I always use the async. reset to set them to a known value, but of course I might have forgotten one, and I also don't know for sure if the used IP cores clear all the registers at power up.

Do you think that the reset is the most likely source of error in this case, or are there other pitfalls I might not be aware of?

kind regards

Christoph