Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

instaciating the same architecture twice gives different results

Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Two instants of same design may differ because of:

(1) different input (make sure all inputs are exactly same. as a test pass same input copy to both).

(2) different output interpretation, e.g. embedded analyser results or DAC paths

(3) timing

(4) power up reset values

(5) user error

(6) fitting error

(7) flaky design

With signaltap you can compare the output at every stage readily