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Altera_Forum
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15 years ago

instaciating the same architecture twice gives different results

Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The powerup don't care defaults to ON in quartus, set it to OFF. => settings => analysis and synthesis => more settings...

With regard to signaltap, it is true it adds further strain on timing but you can use it to exclude DAC differences.

The reset sequencer can be made variable on the two instants until both work.

also make sure all important signals are reset to known values.