Initialize ram block with different filename using generate loop.

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How to solve this problem?

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If you were writing VHDL, I would recommend writing a function that takes the loop parameter (integer) and returns a string. I'm sure the same is possible with Verilog/SystemVerilog.

Cheers,

Dave

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If you were writing VHDL, I would recommend writing a function that takes the loop parameter (integer) and returns a string. I'm sure the same is possible with Verilog/SystemVerilog.

Cheers,

Dave

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Perhaps the constant function is a solution, but how can i convert the loop parameter into string?

I found the $sformatf can do that, but the system function is not available in constant function.

Can you give me a short example on that?

$sformatf will work as a constant function as long all of its arguments are constants in Modelsim.

The alternative is to have the generate loop block of code execute the code that does the initialization, then it doesn't need to be a constant.

genvar I;
for (I=0;i<NUM;i++) begin : block
  RAM inst(...);
  initial $readmemh($sformatf("file%2d.dat",I),inst.mem_inst);
end : block