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Altera_Forum
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12 years ago

Initialize ram block with different filename using generate loop.

I want to generate several instance of ram block and initialize it with different filename in Quartus II (Verilog 2001) It seems that verilog does not support 2D parameter array, and part select o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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If you were writing VHDL, I would recommend writing a function that takes the loop parameter (integer) and returns a string. I'm sure the same is possible with Verilog/SystemVerilog.

Cheers,

Dave

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Perhaps the constant function is a solution, but how can i convert the loop parameter into string?

I found the $sformatf can do that, but the system function is not available in constant function.

Can you give me a short example on that?