Forum Discussion

k_dz's avatar
k_dz
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Inferring RAM with byte-enable from parametrized SystemVerilog

I'm trying to write RAM with byte-enable inputs with parametrizable number of bytes. Templates for RAM with byte-enable in Lite and Standard versions of Quartus assume a certain number of bytes in a ...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

found a better solution for Quartus Std., use generate for instead of simple for loop.

genvar i;
generate for (i = 0; i < NUM_BYTES; i++) begin : gen_be
   always@(posedge clk)
      if(we & be[i]) ram[waddr][i] <= wdata[i*BYTE_WIDTH +: BYTE_WIDTH];
end
endgenerate

   always@(posedge clk)
   begin
      q <= ram[raddr];
   end

Regards
Frank

k_dz's avatar
k_dz
Icon for New Contributor rankNew Contributor
1 year ago

Although it uses dedicated memory resources and does not require repeating a single line, I'm not sure it's a better solution. In my testing it maps to NUM_BYTES separate M10K blocks and I couldn't find a way to convert it to write-first/"read new data", as Quartus requires blocking assignments to infer such same-port read-during-write behaviour.

I know that I can just generate N separately driven RAM modules, each storing the i-th byte forming N-byte word, but that is just wasteful in many cases.