Include additional VHDL syntax rules - Linting

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I'm trying to "upgrade" the syntax rules with formal rules likewise using capital letters for VHDL, i.e. vhld reserved keywords shall not only be highlighted in a defined color but shall also be checked to be written completely in captial letters to be conform with coding style guideline for the project.

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C'mon, why would you want your code shouting at you ? :)

Cheers,

Dave

Carl, One suggestion would be to consider using Python to create a custom linting solution employing regular expressions to parse the VHDL code. I have thought of doing this myself in the past. The case insensitivity of VHDL makes linting definitely a more custom solution. There is also the pygments highlighter, written in Python, that you could use in conjunction with your regular expressions to produce HTML or Latex output with corresponding text highlighted.

I've often thought it would be nice to write a program that would lex/parse your VHDL code, then produce a document that was a documentation summary, which included a block diagram showing all the I/O of the module being documented. The main thing required here would be to lex for the "port" in the vhdl file and then build the graphics in the document accordingly.

Best, James

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Hi,

I'm trying to "upgrade" the syntax rules with formal rules likewise using capital letters for VHDL, i.e. vhld reserved keywords shall not only be highlighted in a defined color but shall also be checked to be written completely in captial letters to be conform with coding style guideline for the project. I'm aware this (and much more) is covered by LINT tools like ALINT, Spyglasss, ... but I need some lower cost solution... Best would be to "upgrade" the rules in Quartus Analysis...

Any ideas?

Thanks a lot,

Carlhermann

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Hi,

I'm aware this is a custom requirement, which may look strange for most programmers. I also got a comment of a collegue (doing most of his programming in C/C++) that this (capital letters) would negatively influence the efficiency of typing and thus extend the time required for code writing :-). Nevertheless the color option to highlight VHDL keywords is useless on b/w printers.

Besides this there are other "regulations" likewise indend for nested if - then - else,... to increase readability.

Well - the intention is to implement the DO-254 User Group position paper on VHDL code with some extras.

Tools doing the job are some bucks extra... I do not doubt the tools are (more or less) worth these bucks, but as my job is not writing VHDL all the time, spending these extra bucks is not my primary option.

@Dave: I'm over 40years now, thus my ears are degrading and I need my code to shout to catch my attention ^.^

@James: I think I came across tools doing stuff like that (converting the textual input of VHDL with mapped modules to some graphical representation is even an option in Quartus) while the result might be less easy to read than the VHDL code itself.. Especially if some signals are routed all across the design...

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Hi,

@Dave: I'm over 40years now, thus my ears are degrading and I need my code to shout to catch my attention ^.^

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I've been doing VHDL design for 20 odd years now and my eyesight isn't getting any better. I think that the easiest style to parse

is well spaced and indented code in lower case with an _odd_ thing in uppercase. I use uppercase for constants but pretty much

everything else is in lower case.

And as 'yer man said it'll make code entry a lot more hassle if keywords etc are in uppercase.

Nial.

You can use the sigasi (http://www.sigasi.com/) editor : it prints keywords in bold and uses different shades of gray for other words. You can change these settings to your own likings.

And it also formats and indents your code, the only drawback is that you cannot change the formatting rules (I keep on asking Sigasi to change this ...). The good thing is that this also works in the 'free' version. You may want to print to a pdf-file using A3 (or some user-define size of) paper to get a reasonable page-filling.