Include additional VHDL syntax rules - Linting

Hi,

I'm aware this is a custom requirement, which may look strange for most programmers. I also got a comment of a collegue (doing most of his programming in C/C++) that this (capital letters) would negatively influence the efficiency of typing and thus extend the time required for code writing :-). Nevertheless the color option to highlight VHDL keywords is useless on b/w printers.

Besides this there are other "regulations" likewise indend for nested if - then - else,... to increase readability.

Well - the intention is to implement the DO-254 User Group position paper on VHDL code with some extras.

Tools doing the job are some bucks extra... I do not doubt the tools are (more or less) worth these bucks, but as my job is not writing VHDL all the time, spending these extra bucks is not my primary option.

@Dave: I'm over 40years now, thus my ears are degrading and I need my code to shout to catch my attention ^.^

@James: I think I came across tools doing stuff like that (converting the textual input of VHDL with mapped modules to some graphical representation is even an option in Quartus) while the result might be less easy to read than the VHDL code itself.. Especially if some signals are routed all across the design...