Include additional VHDL syntax rules - Linting

Carl, One suggestion would be to consider using Python to create a custom linting solution employing regular expressions to parse the VHDL code. I have thought of doing this myself in the past. The case insensitivity of VHDL makes linting definitely a more custom solution. There is also the pygments highlighter, written in Python, that you could use in conjunction with your regular expressions to produce HTML or Latex output with corresponding text highlighted.

I've often thought it would be nice to write a program that would lex/parse your VHDL code, then produce a document that was a documentation summary, which included a block diagram showing all the I/O of the module being documented. The main thing required here would be to lex for the "port" in the vhdl file and then build the graphics in the document accordingly.

Best, James

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Hi,

I'm trying to "upgrade" the syntax rules with formal rules likewise using capital letters for VHDL, i.e. vhld reserved keywords shall not only be highlighted in a defined color but shall also be checked to be written completely in captial letters to be conform with coding style guideline for the project. I'm aware this (and much more) is covered by LINT tools like ALINT, Spyglasss, ... but I need some lower cost solution... Best would be to "upgrade" the rules in Quartus Analysis...

Any ideas?

Thanks a lot,

Carlhermann

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