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Altera_Forum's avatar
Altera_Forum
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12 years ago

IIR filter implementation in verilog

does anyone have the idea how to get rid of extra bits that comes in IIR filter due to feedback?each time the feedback occurs the inputs bits gets changed and so is the case with the output bits?I just need the concept of setting this bit width in IIR filter input ant output sides.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi.

    You have to truncate several least significant bits after addtion or to round the result, rounding is better (less level of self noise at the same data width). Actually data and coefficients resolution in IIR filters isn't a simple issue, because it influences filter characteristics and it's stability, self-noise, limit cycle probability and it's maximum level (under certain conditions IIR could generate a periodic signal at it's output even if input signal is zero).

    Have a nice day.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanx! I will try it. one more thing I want to ask is that I am using a twin pipe serial parallel multiplier for multiplication in filter.I am not getting any idea to write its behavioural code! if you have any sample code for this multiplier please do post it....