IDENTIFYING THE ECC BYTE IN 40 bit DATA BUS OF EMIF CONTROLLER of ARRIA 10 HPS

Dear All,

Designing ARRIA 10 board with 32 bit DDR4 interface (2 components - 4Gb each (256 X 16)) and the third component used for ECC - total 40 bit on the HPS side.

I am unable to identify the ECC byte of the 40 bit databus of DDR4 EMIF controller on the HPS Side of ARRIA 10 from teh Quartus project. This may sound naïve but I am in that problem.

Although we are aware that lane 3 of 2K bank will be the ECC Byte for 32 bit DDR interface with 8 bit ECC but we are unable to understand teh same from pin files or RTL implementation.

The reason for such query is that till date we used lower byte of 3rd DDR chip as ECC on our hardware and the controller side also as DQ(32:39) data width. But now in ARRIA 10 N3F40 SX, PCB routing is such that DQ(0:7) looks to be a better choice for ECC which is connected to lower byte of 1st DDR chip and is mapped to 3rd lane of 2K bank. Quartus accepts this formation but I want to confirm the same from Quartus that lowest byte of DQ bus is ECC DQ(0:7) and the remaining 32 bit is data (DQ(8:39)) . Quartus project assigns DQ(0:7) to 2K bank lane 3 but how do we know that it is actually ECC byte from project, RTL or otherwise....

Can some please help us understand the same ....