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Altera_Forum's avatar
Altera_Forum
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9 years ago

Identifier "UNSIGNED" is not directly visible

i have used the following libaries

LIBRARY IEEE;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.numeric_std.all;

still the error in modelsim shows :

** Error: G:/vhdl code/vhdl code/dwt_main.vhd(30): (vcom-1078) Identifier "UNSIGNED" is not directly visible.

Potentially visible declarations are:

ieee.NUMERIC_STD.UNSIGNED (subtype declaration)

ieee.std_logic_arith.UNSIGNED (type declaration)

** Error: G:/vhdl code/vhdl code/dwt_main.vhd(31): (vcom-1078) Identifier "SIGNED" is not directly visible.

Potentially visible declarations are:

ieee.NUMERIC_STD.SIGNED (subtype declaration)

ieee.std_logic_arith.SIGNED (type declaration)

how to solve it

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    line 30 TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED(7 DOWNTO 0);

    line 31 TYPE buf_ary_d IS ARRAY (NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0);
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Try leaving out: 

    USE ieee.std_logic_arith.all;

    It is a deprecated library, you will find everything you need in: 

    USE ieee.numeric_std.all;
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    i have already included these libraries above

    i have used the following libaries

    LIBRARY IEEE;

    USE ieee.std_logic_1164.all;

    USE ieee.std_logic_arith.all;

    USE ieee.numeric_std.all;
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Try just the following:

    library ieee ;

    use ieee.std_logic_1164.all ;

    use iee.numeric_std.all;
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    yes it worked ....for the time being that error got solved.....thanks

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The error is caused by numeric_std and std_logic_arith both declaring the unsigned and signed types, meaning you need to specifically state which one to use:

    eg.

    signal a : numeric_std.unsigned;

    signal b : std_logic_arith.unsigned;

    The problem is they are not the same type, and VHDL rules mean that two types with the same name in the same namespace become invisible.

    std_logic_arith is not a standard VHDL library - and so should not be used.