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Altera_Forum
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10 years ago

Identifier "UNSIGNED" is not directly visible

i have used the following libaries LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; still the error in modelsim shows : ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The error is caused by numeric_std and std_logic_arith both declaring the unsigned and signed types, meaning you need to specifically state which one to use:

eg.

signal a : numeric_std.unsigned;

signal b : std_logic_arith.unsigned;

The problem is they are not the same type, and VHDL rules mean that two types with the same name in the same namespace become invisible.

std_logic_arith is not a standard VHDL library - and so should not be used.