I am using quartus pro 18.1 I get a error unconstrained ports can only be associated in whole if I cast a unconstrained std_logic_vector to an unsigned for my generic memory

I have memory block I have memory as follows: entity memory is port ( clk : in std_logic; din : std_logic_vector; wr : in std_logic; dout: std_logic_vector ); When I instantiate for exa...