Forum Discussion
I am trying to modify and compile the De1-SoC Computer System that Intel has created, however I am getting this error when I compile my system. This error appears both on the original Computer System and the one I modified. Any help?
Problem Details
Error:
Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_register_packer_clk_region_callback.cpp, Line: 171
target_gid != DEV_ILLEGAL_GLOBAL_ID
Stack Trace:
0x2e507: FSV_REGISTER_PACKER_CLK_REGION_CALLBACK::is_io_packing_feasible + 0x417 (fitter_fsv)
0x13ffa6: FSAC_FF_RP_LEGALITY_CALLBACK_MGR::do_io_packing_feasibility_callbacks + 0x46 (FITTER_FSAC)
0x276380: FSAC_FF_REGISTER_PACKER_OP_BODY::try_to_pack_fast_inputs + 0x4b0 (FITTER_FSAC)
0x274782: FSAC_FF_REGISTER_PACKER_OP_BODY::pack_registers_due_to_io_fast_register_and_pll_source_sync_mode_assignments + 0xcd2 (FITTER_FSAC)
0x275147: FSAC_FF_REGISTER_PACKER_OP_BODY::pack_registers_opportunistically + 0x1e7 (FITTER_FSAC)
0x26115: fsv_do_opportunistic_register_packing + 0x1b5 (fitter_fsv)
0x23f44: FSV_EXPERT::fitter_preparation_post_fpp + 0x4b4 (fitter_fsv)
0x1e0df: FSV_EXPERT_BASE::fitter_preparation_run_family_fitter_preparation + 0x4f (fitter_fsv)
0x1dbd8: FSV_EXPERT_BASE::fitter_preparation + 0x68 (fitter_fsv)
0x1e830: FSV_EXPERT_BASE::invoke_fitter + 0x3b0 (fitter_fsv)
0x1c952: fsv_execute + 0x22 (fitter_fsv)
0xe910: fmain_start + 0x900 (FITTER_FMAIN)
0x41b1: qfit_execute_fit + 0x1bd (comp_qfit_legacy_flow)
0x5384: QFIT_FRAMEWORK::execute + 0x2a0 (comp_qfit_legacy_flow)
0x267f: qfit_legacy_flow_run_legacy_fitter_flow + 0x1c7 (comp_qfit_legacy_flow)
0x14410: TclInvokeStringCommand + 0xf0 (tcl86)
0x161e2: TclNRRunCallbacks + 0x62 (tcl86)
0x17a65: TclEvalEx + 0xa65 (tcl86)
0xa6f8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
0xa5646: Tcl_EvalFile + 0x36 (tcl86)
0x12606: qexe_evaluate_tcl_script + 0x376 (comp_qexe)
0x11864: qexe_do_tcl + 0x334 (comp_qexe)
0x16755: qexe_run_tcl_option + 0x585 (comp_qexe)
0x380c3: qcu_run_tcl_option + 0x1003 (comp_qcu)
0x160aa: qexe_run + 0x39a (comp_qexe)
0x16e51: qexe_standard_main + 0xc1 (comp_qexe)
0x2233: qfit2_main + 0x73 (quartus_fit)
0x12e98: msg_main_thread + 0x18 (CCL_MSG)
0x1467e: msg_thread_wrapper + 0x6e (CCL_MSG)
0x16660: mem_thread_wrapper + 0x70 (ccl_mem)
0x12761: msg_exe_main + 0xa1 (CCL_MSG)
0x287e: __tmainCRTStartup + 0x10e (quartus_fit)
0x17bd3: BaseThreadInitThunk + 0x13 (KERNEL32)
0x6ce50: RtlUserThreadStart + 0x20 (ntdll)
End-trace
Executable: quartus_fit
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 18.1.0
Build: 625
Edition: Lite Edition
2 Replies
- KennyT_altera
Super Contributor
Can you check if you attempt to access HPS dedicated pins from SignalTAP which can connect to FPGA logic only.
Some HPS peripherals can be observed via SignalTAP when interface is routed via FPGA, but this might not your case according to HPS setting of SD/MMC.
- NRoba
New Contributor
Thank you, that must have been the issue I believe! I simply removed the signaltap file from the project. Runs just fine now!