Forum Discussion

NRoba's avatar
NRoba
Icon for New Contributor rankNew Contributor
6 years ago

I am trying to modify and compile the De1-SoC Computer System that Intel has created, however I am getting this error when I compile my system. This error appears both on the original Computer System and the one I modified. Any help?

Problem Details Error: Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_register_packer_clk_region_callback.cpp, Line: 171 target_gid != DEV_ILLEGAL_GLOBAL_ID Stack Trace: 0x2e...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Can you check if you attempt to access HPS dedicated pins from SignalTAP which can connect to FPGA logic only.

Some HPS peripherals can be observed via SignalTAP when interface is routed via FPGA, but this might not your case according to HPS setting of SD/MMC.

  • NRoba's avatar
    NRoba
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you, that must have been the issue I believe! I simply removed the signaltap file from the project. Runs just fine now!