I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi,

You mentioned that this problem was already solved in the past by upgrading the 13.1 Quartus II version. May I know what is the version that you did not see the error?

Thanks.

Best regards,

KhaiY

The Quartus version I use on my Windows 7 desktop is Quartus II 32-bit version 13.1.4 Build 182 03/12/2014 SJ Web Edition. And is the version that failed to compile above example and others where Xilinx Ise 14.6 had no problem with to create the right RTL circuits.

And below is another example of VHDL code that perfectly works in Xilinx ISE (not Spartan3E but with higher FPGA's only!) but never works in Quartus:

--BRAM_16x2 page194 Vaibbhav Taraate.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity BRAM_16x2 is

port (q_out : out std_logic_vector (1 downto 0);

write_en : in std_logic;

clk: in std_logic;

d_in: in std_logic_vector (1 downto 0);

a_in: in std_logic_vector (3 downto 0));

end BRAM_16x2;

architecture BRAM_arch of BRAM_16x2 is

component BRAM_16x1S is

port(O : out std_logic;

D: in std_logic;

A3, A2, A1, A0: in std_logic;

WE, W_CLK: in std_logic);

end component;

begin

U0: BRAM_16x1S port map (O =>q_out(0), WE =>write_en, W_CLK =>clk, D =>d_in(0),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

U1: BRAM_16x1S port map (O =>q_out(1), WE => write_en, W_CLK => clk, D =>d_in(1),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

end BRAM_arch;

--------------Which gives following error rapport in Quartus II 13.1 but works in ISE! -------

Warning (20028): Parallel compilation is not licensed and has been disabled

Warning (12125): Using design file bram_16x2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project

Info (12022): Found design unit 1: BRAM_16x2-BRAM_arch

Info (12023): Found entity 1: BRAM_16x2

Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S"

Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S"

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings

Error: Peak virtual memory: 393 megabytes

Error: Processing ended: Mon May 11 17:13:47 2020

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:02

Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 2 warnings

Hi,

I understand that the original RTL mismatch problem is solved by upgrading the software to Quartus II 32-bit version 13.1.4 Build 182 03/12/2014 SJ Web Edition.

For the new error below, can you share the full design.QAR file for investigation? To create the design, click on Project > Archive Project > Archive

Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S"

Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S"

Thanks.

Best regards,

KhaiY

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

No sadly I have just quit for the time being unable to solve the Quartus II issues presented above. I also use Xilinx that works where Quartus completely failed in the given examples. And another problem arose that made me get stuck in my Quartus II version in that it apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations and the to simulate input data. It apparently never is intuitive which would make starting to use Quartus much easier. Never knowing (all off-line without on-line connection) how to use Quartus II correctly. Apparently I still have to manually set all input and outputs before any simulation is possible in Quartus? I keep reading books on VHDL , the best one yet was Vaibbhav Taraate's PLD Based Design with VHDL, but still I need another book on how to use Quartus. (the BRAM examples and other examples from that book failed in Quartus but worked in Xilinx ISE!). So at the moment I just keep on reading other books on VHDL too and didn't get any further where Quartus is concerned.

Hi,

Do you still see the error below? If yes, can you provide the design.qar for investigation?

Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S"

Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S"

For the new question on simulation: It apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations and the to simulate input data. can you open a new forum post to make sure that there is only one question in one post? This helps to reduce confusion to the other users who have the same error and helps them to find the solution to each of the error/question easily.

Thanks.

Best regards,

KhaiY

Sadly even saving the QAR file of the BRAM16x2 example failed to complete successfully. Therefore I also included the errorlog files into a combined rar file. Hereby added. And I will try to open the Quartus II simulation question into the correct Forum links later on.

Hi,

The rar file is corrupted. Could you reattach?

Thanks.

Best regards,

KhaiY

Hi Albert,

Can you send the entire project directory in ZIP?

Thanks.

Best regards,

KhaiY