I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

No sadly I have just quit for the time being unable to solve the Quartus II issues presented above. I also use Xilinx that works where Quartus completely failed in the given examples. And another problem arose that made me get stuck in my Quartus II version in that it apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations and the to simulate input data. It apparently never is intuitive which would make starting to use Quartus much easier. Never knowing (all off-line without on-line connection) how to use Quartus II correctly. Apparently I still have to manually set all input and outputs before any simulation is possible in Quartus? I keep reading books on VHDL , the best one yet was Vaibbhav Taraate's PLD Based Design with VHDL, but still I need another book on how to use Quartus. (the BRAM examples and other examples from that book failed in Quartus but worked in Xilinx ISE!). So at the moment I just keep on reading other books on VHDL too and didn't get any further where Quartus is concerned.