Occasional Contributor
Occasional ContributorAnd below is another example of VHDL code that perfectly works in Xilinx ISE (not Spartan3E but with higher FPGA's only!) but never works in Quartus:
--BRAM_16x2 page194 Vaibbhav Taraate.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BRAM_16x2 is
port (q_out : out std_logic_vector (1 downto 0);
write_en : in std_logic;
clk: in std_logic;
d_in: in std_logic_vector (1 downto 0);
a_in: in std_logic_vector (3 downto 0));
end BRAM_16x2;
architecture BRAM_arch of BRAM_16x2 is
component BRAM_16x1S is
port(O : out std_logic;
D: in std_logic;
A3, A2, A1, A0: in std_logic;
WE, W_CLK: in std_logic);
end component;
begin
U0: BRAM_16x1S port map (O =>q_out(0), WE =>write_en, W_CLK =>clk, D =>d_in(0),
A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));
U1: BRAM_16x1S port map (O =>q_out(1), WE => write_en, W_CLK => clk, D =>d_in(1),
A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));
end BRAM_arch;
--------------Which gives following error rapport in Quartus II 13.1 but works in ISE! -------
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (12125): Using design file bram_16x2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info (12022): Found design unit 1: BRAM_16x2-BRAM_arch
Info (12023): Found entity 1: BRAM_16x2
Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S"
Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S"
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 393 megabytes
Error: Processing ended: Mon May 11 17:13:47 2020
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 2 warnings
