Huge reduce in logic usage when megafunction is instantiated

When you instantiate each component on their own, synthesis knows nothing about their inputs and outputs and generated a perfectly generic component.

However, when you begin putting them together on real circuits, synthesis is, sometimes, able to deduce that some output signals won't be used and that some input signals are constant (or related) and thus optimize the design.

Considering that you're using switches to change the inputs, I'm betting that your adder's inputs are far short of the ~(2^32)^2 possible combinations supported by a single precision fp adder.

Hi rbugalho,

Thanks for your reply. That makes sense but is there any documentation about this that I can read about? Because I don't know much about the fitting and synthesis. Actually what do you mean by the "some output signals wont be used and that some input signals are constant" part? I don't understand how the input signals would be constant and why the output signals won't be used.

Yea I needed around 66 inputs and didn't bother with the IDE header expansion thing, so I just wired them in VHDL since I was just playing around with it.

Best regards,

Chris

The synthesis tool will analyze your entire design.

It will (sometimes) be able to figure out that some signals will be always 0 or always 1. Thus, logic that is driven by those signals will be optimized.

Conversly, it may also figure out that the value of some signals never affect any of the design's (top level) outputs. Thus, it will optimize away the logic required for those signals.

There isn't much documentation about this, AFAIK. The tools just try to optimize everything they can and they keep getting smarter about it every year.

--- Quote Start ---

Simply ALTFP_ADD_SUB can't reduce it's LE requirement to said 400 LEs without omitting a considerable part of it's function, e.g number of calculated bits. So rbugalho obviously assumed, you must have removed part of it's arithmetic function by not completely connecting all in- and outputs of the Megafunction. I agree that it's the only plausible explanation for your results.

--- Quote End ---

Thanks for your reply, FvM. But how do I check whether I omitted a part of it's function?

I just used the .cmp files to instantiate it and assigned all the signals to the Port map.

I assigned values to the inputs into the megafunction by code and it manages to calculate the correct result, so I guess it should be functional.

Thanks again,

Chris

--- Quote Start ---

The synthesis tool will analyze your entire design.

It will (sometimes) be able to figure out that some signals will be always 0 or always 1. Thus, logic that is driven by those signals will be optimized.

Conversly, it may also figure out that the value of some signals never affect any of the design's (top level) outputs. Thus, it will optimize away the logic required for those signals.

There isn't much documentation about this, AFAIK. The tools just try to optimize everything they can and they keep getting smarter about it every year.

--- Quote End ---

Thanks for explaining, I think I get it now!

Yea it's amazing how people think of ways how to improve these stuff.

Best regards,

Chris

Guys!

I finally got it! As I kept reading your posts over and over again, it suddenly hit me!

It was because I forced the inputs to certain values in software, that's why it compiled to be much smaller due to the optimisations it did!

Thanks a lot guys, this question's kinda been bugging me whole day like a bad song in my head. Now I can rest well. Haha.

Best regards,

Chris