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Altera_Forum
Honored Contributor
15 years agoHi rbugalho,
Thanks for your reply. That makes sense but is there any documentation about this that I can read about? Because I don't know much about the fitting and synthesis. Actually what do you mean by the "some output signals wont be used and that some input signals are constant" part? I don't understand how the input signals would be constant and why the output signals won't be used. Yea I needed around 66 inputs and didn't bother with the IDE header expansion thing, so I just wired them in VHDL since I was just playing around with it. Best regards, Chris