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The synthesis tool will analyze your entire design.
It will (sometimes) be able to figure out that some signals will be always 0 or always 1. Thus, logic that is driven by those signals will be optimized.
Conversly, it may also figure out that the value of some signals never affect any of the design's (top level) outputs. Thus, it will optimize away the logic required for those signals.
There isn't much documentation about this, AFAIK. The tools just try to optimize everything they can and they keep getting smarter about it every year.
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Thanks for explaining, I think I get it now!
Yea it's amazing how people think of ways how to improve these stuff.
Best regards,
Chris
Honored Contributor
