How to write a testbench which can initialize sub-module?

Here is my simple test code.

parameter MEM_SIZE = 1024;

reg [7:0] one_A[0:MEM_SIZE-1];

initial begin

for (int i=0; i<MEM_SIZE; i++)

one_A[i] = i + 10;

end

ertss,

a module's internal variables are not accessible from other modules.

Thus, you need to work around that.

You can either initialize the ram within the "memory" module itself or you can add some interface to the "memory" module that can write into the memory.

As rbugalho hinted, you need to "manually" write to the memory module to initialize it... For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle.

Altera's devices (and probably other FPGA vendors too) doesn't support asynchronous clearing/resetting of memory contents, probably because it is too expensive to implement on silicon.

I don't understand some of the statements.

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For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle.

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But the original question is referring to an initial block, which is simply inferring a constant initialization of a RAM, similar to a *.mif file. Furthermore, the discussion is about simulation rather than synthesis. In simulation, "everything goes".

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a module's internal variables are not accessible from other modules

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Generally, Verilog allows access through hierachical names. So the question is, why it's not working here.