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Altera_Forum
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15 years ago

How to write a testbench which can initialize sub-module?

Hi all, I need to simulate with the topmodule of my design. But i have to initialize the memory value in the memory sub-module. How can i do that in the testbench in for the top-module? ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

As rbugalho hinted, you need to "manually" write to the memory module to initialize it... For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle.

Altera's devices (and probably other FPGA vendors too) doesn't support asynchronous clearing/resetting of memory contents, probably because it is too expensive to implement on silicon.