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Altera_Forum
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15 years ago

How to write a testbench which can initialize sub-module?

Hi all, I need to simulate with the topmodule of my design. But i have to initialize the memory value in the memory sub-module. How can i do that in the testbench in for the top-module? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ertss,

a module's internal variables are not accessible from other modules.

Thus, you need to work around that.

You can either initialize the ram within the "memory" module itself or you can add some interface to the "memory" module that can write into the memory.