How to write a testbench which can initialize sub-module?

I don't understand some of the statements.

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For example, if you want to initialize it to all std_logic '0's, you need to *write* to the memory the value of '0' at every clock cycle.

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But the original question is referring to an initial block, which is simply inferring a constant initialization of a RAM, similar to a *.mif file. Furthermore, the discussion is about simulation rather than synthesis. In simulation, "everything goes".

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a module's internal variables are not accessible from other modules

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Generally, Verilog allows access through hierachical names. So the question is, why it's not working here.