Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to use OCT calibration for Cyclone III DDR SDRAM interface

I am using the High Performance Controller (HPC) to interface to a single DDR SDRAM located close to a Cyclone III FPGA and I am running at a 125 MHz memory clock speed. By default the HPC sets up the DDR IOs as SSTL-2 Class I and sets a current strength of 12mA for all the SDRAM pins.

This works ok but to make the interface more robust I would like to be able to use the Cyclone III OCT with calibration feature and set all the pins to 50 Ohms. However if I set OUTPUT_TERMINATION to "SERIES 50 OHM WITH CALIBRATION" for each SDRAM pin then the compilation fails with an error in the fitter of "Current Strength logic option is set to 12mA for pin ... but setting is not allowed with a Termination assignment"

If I comment out the 12mA CURRENT_STRENGTH_NEW assigments then the compilation finishes but I get critical warnings from TimeQuest for some of the pins (DQ, DQS, DM, CK, CKN) of "Pin ... must have its Current Strength logic option set to 12mA instead of Default" and TimeQuest reckons that the timing requirements are not met with the HPC clock rate being "limited due to minimum port rate restriction (tmin)".

So how can I get this to both compile and keep TimeQuest happy? Is it a simple matter of letting TimeQuest know somehow that the current strength is stronger than the default. Or is TimeQuest making a valid point and it is just not possible to run the RAM interface at 125MHz with a 50 Ohm impedance? Any help would be greatly appreciated.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    - Drive strength and OCT are mutually exclusive assignments(in essence the drive strength is controlled by a resistor(transistors) and vice-versa. To a certain degree the two settings are just different ways of describing the same thing. Because of that you can't use both assignments. (I've never seen a direct correlation though, such as 12ma = an OCT value of# #.)

    - The DDR2 timing is generally done with a "macro timing model". What this means is the entire interface was evaluated and guaranteed to work. (This allows for better performance. With the usual "micro timing model" when a lot of small micro-parameters are added together, each one has a little guardband, and as a whole the guardband gets unrealistic. So the macro timing model allows for higher performance. THe problem with the macro timing model is that you can't deviate from what was tested, because there's not modeling of that. So by changing something that you think should make the interface work better, it has to give a message that's basically saying you're using it in a way that doesn't correlate to the macro timing model, and so we can't do true timing analysis.

    So, you can choose to ignore this if you want, or go back to the old setting and leave it as is.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks Rysc. It seems a shame that the calibration feature cannot be used but I understand your comments.

    My only follow-up question would be what is the "macro timing model" expecting externally in the way of series termination resistors? I am directly connecting to all the SDRAM pins with the exception of the DQ and DQS pins which have 22R series resistors next to the SDRAM, and there is a 100R termination across the two clock pins. Is this all I need?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Although dedicated to DDR2 memory, Altera AN408, that discusses in detail the properties of different SSTL termination schemes, is also interesting for DDR memory.

    As a major difference, DDR doesn't provide parallel termination (ODT = on-chip dynamic termination) resistors. Thus according to SSTL class I scheme, parallel termination resistors are basically required for all address, control, dq and dqs lines.

    With short traces and at reduced clock speeds, an unterminated operation may be possible though.

    P.S.: Regarding the previous question of 50 ohm versus SSTL IO standard:

    DDR memory interface requires a voltage referenced standard. For this reason, only SSTL class x can be used. The calibration aspect (exactly meeting the nominal impedance) is only of minor relevance in my opinion.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks for your comments. My conclusion is that I will return to the standard 12mA uncalibrated drive strength and risk not having any parallel termination. I think this is justified because my matched track lengths are quite short (42mm for address/control, 33mm for data) and the SDRAM is quite fast (200 MHz part clocked at 125 MHz). Thanks again for your help.