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Altera_Forum
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16 years ago

How to use OCT calibration for Cyclone III DDR SDRAM interface

I am using the High Performance Controller (HPC) to interface to a single DDR SDRAM located close to a Cyclone III FPGA and I am running at a 125 MHz memory clock speed. By default the HPC sets up th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for your comments. My conclusion is that I will return to the standard 12mA uncalibrated drive strength and risk not having any parallel termination. I think this is justified because my matched track lengths are quite short (42mm for address/control, 33mm for data) and the SDRAM is quite fast (200 MHz part clocked at 125 MHz). Thanks again for your help.