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Altera_Forum
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16 years ago

How to use OCT calibration for Cyclone III DDR SDRAM interface

I am using the High Performance Controller (HPC) to interface to a single DDR SDRAM located close to a Cyclone III FPGA and I am running at a 125 MHz memory clock speed. By default the HPC sets up th...
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Altera_Forum
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16 years ago

Thanks Rysc. It seems a shame that the calibration feature cannot be used but I understand your comments.

My only follow-up question would be what is the "macro timing model" expecting externally in the way of series termination resistors? I am directly connecting to all the SDRAM pins with the exception of the DQ and DQS pins which have 22R series resistors next to the SDRAM, and there is a 100R termination across the two clock pins. Is this all I need?