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Altera_Forum
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16 years ago

How to use OCT calibration for Cyclone III DDR SDRAM interface

I am using the High Performance Controller (HPC) to interface to a single DDR SDRAM located close to a Cyclone III FPGA and I am running at a 125 MHz memory clock speed. By default the HPC sets up th...
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Altera_Forum
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16 years ago

Although dedicated to DDR2 memory, Altera AN408, that discusses in detail the properties of different SSTL termination schemes, is also interesting for DDR memory.

As a major difference, DDR doesn't provide parallel termination (ODT = on-chip dynamic termination) resistors. Thus according to SSTL class I scheme, parallel termination resistors are basically required for all address, control, dq and dqs lines.

With short traces and at reduced clock speeds, an unterminated operation may be possible though.

P.S.: Regarding the previous question of 50 ohm versus SSTL IO standard:

DDR memory interface requires a voltage referenced standard. For this reason, only SSTL class x can be used. The calibration aspect (exactly meeting the nominal impedance) is only of minor relevance in my opinion.