Forum Discussion
CalvinJoaz_P_Intel
Contributor
7 years agoHi Kian,
Good day.
Kindly try the following steps below for creating new file for the same project.
1) File -> New -> Click 'Verilog HDL File' -> Click 'OK'
2) Click File -> Save As -> Change the File name: Adder_tb.v.
I tried these steps it works for me.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Thank you.