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KTagh
New Contributor
New ContributorHow to stop Quartus Lite automatically naming new files ?
I am currently working on a simple project required for my class in where we build an Adder using Quartus Prime, but the tutorial our professor provided for us was for an older edition. I have succe...
CalvinJoaz_P_Intel
Contributor
ContributorHi Kian,
Good day.
Kindly try the following steps below for creating new file for the same project.
1) File -> New -> Click 'Verilog HDL File' -> Click 'OK'
2) Click File -> Save As -> Change the File name: Adder_tb.v.
I tried these steps it works for me.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Thank you.
