Forum Discussion
Just tried the FFT IP with Quartus 16.1 and ModelSim 10.5b. Generated the FFT with default parameters , generated example design as well as testbench system using Qsys.
Are you sure you have the license for the FFT IP core? This may be due to IP core licensing as well.
When you generate the design and select the generate testbench/simulation files with Verilog option, a simulation folder will be created with the simulator specific scripts.
When you generate the example design, Qsys will create an design example along with all necessary simulation scripts and data.
Invoked ModelSim, changed directory to the generated FFT simulation/mentor or testbench/mentor directory .
Sourced the msim_setup.tcl file in ModelSim command prompt - do msim_setup.tcl
Compiled and Simulated design using the "ld_d" or "ld" command.
ld_d - compile and simulation with debug options
ld- compile and simulate
Was able to simulate the design without any errors. Tried it for both generated design as well as generated example design. It works without any issues.