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Occasional ContributorHow to set SDC constraints with respect to a clock from pll clock mux inputs?
I have two pll clock muxes.Each of them has two different inputs
Outputs from these plls are fed to another mux which selects the input clock to my logic.
I want to set max skew,max delay and min delay constraints for some output signals with respect to the input clocks to the pll muxes.
I tried something as below,but it constraints with respect to clock output of pll muxes.
set_max_skew -from pll_100MHz_1|altpll_component|auto_generated|pll1|clk[0] -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_1|altpll_component|auto_generated|pll1|clk[0]~1 -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_2|altpll_component|auto_generated|pll1|clk[0] -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_2|altpll_component|auto_generated|pll1|clk[0]~1 -to [get_ports {output_sig}] 2.0
4 Replies
Nooraini_Y_IntelFrequent Contributor
Hi,
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.
Regards,
Nooraini
GuaBin_N_IntelContributor
Were those constraints not taken effect or have been ignored completely? Do you have any block diagram to illustrate how your implementation is?
SK_VAI haven't solved the issue yet.Please see the attached figure of clock tree.
out_clk is the clock used for my logic.
I am trying to constrain the outputs wrt Cb1_clk1,Cb2_clk2,Cb2_clk1,Cb2_clk2 separately.
I am able to constrain wrt Cb1_clk and Cb2_clk (output of PLL muxes).
- GuaBin_N_Intel
What are you trying to constrain? Setting clock frequency at that output of MUX or some sort of routing delay between end points.
