Occasional ContributorHow to set SDC constraints with respect to a clock from pll clock mux inputs?
I have two pll clock muxes.Each of them has two different inputs
Outputs from these plls are fed to another mux which selects the input clock to my logic.
I want to set max skew,max delay and min delay constraints for some output signals with respect to the input clocks to the pll muxes.
I tried something as below,but it constraints with respect to clock output of pll muxes.
set_max_skew -from pll_100MHz_1|altpll_component|auto_generated|pll1|clk[0] -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_1|altpll_component|auto_generated|pll1|clk[0]~1 -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_2|altpll_component|auto_generated|pll1|clk[0] -to [get_ports {output_sig}] 2.0
set_max_skew -from pll_100MHz_2|altpll_component|auto_generated|pll1|clk[0]~1 -to [get_ports {output_sig}] 2.0
