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SK_VA
Occasional Contributor
Occasional ContributorHow to set SDC constraints with respect to a clock from pll clock mux inputs?
I have two pll clock muxes.Each of them has two different inputs Outputs from these plls are fed to another mux which selects the input clock to my logic. I want to set max skew,max delay and min d...
Nooraini_Y_Intel
Frequent Contributor
Frequent ContributorHi,
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.
Regards,
Nooraini
