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SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

How to set SDC constraints with respect to a clock from pll clock mux inputs?

I have two pll clock muxes.Each of them has two different inputs Outputs from these plls are fed to another mux which selects the input clock to my logic. I want to set max skew,max delay and min d...
SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I haven't solved the issue yet.Please see the attached figure of clock tree.

out_clk is the clock used for my logic.

I am trying to constrain the outputs wrt Cb1_clk1,Cb2_clk2,Cb2_clk1,Cb2_clk2 separately.

I am able to constrain wrt Cb1_clk and Cb2_clk (output of PLL muxes).