How to set path skew through SDC?

Hi sstrell,

thank you for answer and advices. My project uses a 200 MHz clock internally generated by a PLL starting from a 50MHz external clock. I have constrained the input clock through the “create_clock” SDC command and the PLL output clock through the “create_generated_clock” command. For my project, some LL block are necessary. However, I can try to remove the not-strictly-necessary LLs.

Come back to block A and B. The block A is a generic block (it does something) while the block B is a decoder with the outputs registered. I assign a LL to block A and B. By this way I can see the decoder-registers as a block. Can I match the paths from outputs of the registers of block A (i.e. the outputs of block A) to inputs of block B? I also tried to use registers at the inputs of the decoder, but I can’t match the paths yet (from the outputs of block A registers to the inputs of block B registers).