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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to pass physic ports "CLOCK_50" to components

Hi, I'm new on this( my first day), I'm trying to make a simple led counter but when I try to pass the clock to the counter I get the error:

Error (10349): VHDL Association List error at Ledsv2.vhd(48): formal "CLOCK_50" does not exist

Some help pleas, I've spend all afternoon looking for solutions.

My code is in VHDL and very Simple. I put it down this lines, there are only two files, the core is LEDsv2.vhd and the Counter is Comptador.vhd

I have more errors but I hope be able correct them by my self.

Thanks

taquion

file: LEDsv2.vhd:

---------------------------------

--

-- Segundo intento Leds

--

-- DE2-115

--

---------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity Ledsv2 is

port(

signal LEDR : out std_logic_vector (17 DOWNTO 0);

signal CLOCK_50 : in std_logic;

signal SW : in std_logic_vector (17 DOWNTO 0);

signal KEY : in std_logic_vector (3 DOWNTO 0)

);

signal CLK : std_logic;

end Ledsv2;

architecture behavior of Ledsv2 is

component Comptador is

port(

signal CLK_comp: in std_logic;

signal nReset : in std_logic;

signal q_out : out std_logic_vector (7 downto 0)

);

end component;

-- Variables Principales

type estados is( S0, S1);

signal stat_act,estat_next : estados;

signal cuentas : std_logic_vector (7 downto 0);

begin

Mapeig_Comptador: Comptador port map (

CLOCK_50 => CLK_comp,

KEY(0) => nReset,

q_out => cuentas -- ms

);

-- Programa

Llums: process (cuentas,state,KEY(0))

begin

if (KEY(0)='0') then

nReset <= '0';

LEDR <=(others=> '0');

state <= S0;

else

case state is

when S0 =>

if (cuentas=250) then

state <= S1;

nReset <= '0';

end if;

when S1 =>

if(LEDR=262144) then

LEDR <= (others => '0');

else

LEDR <= LEDR+'1';

end if;

state <= S0;

when others => null;

end case;

end if;

end process;

end behavior;

-----------------------------------

file: Comptador.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.numeric_std.all;

entity Comptador is

port(

CLK_comp : in std_logic;

nReset : in std_logic;

q_out : out std_logic_vector (7 downto 0)

);

end Comptador;

architecture arch_Comptador of Comptador is

signal q_aux : std_logic_vector (7 downto 0);

signal cuenta: std_logic_vector (15 downto 0);

begin

process(CLK_comp,nReset)

begin

if(nReset='0') then

q_aux <=(others => '0');

elsif (rising_edge(CLK_comp)) then

if(cuenta= 50000) then

cuenta <=(others => '0');

q_aux <= q_aux + '1';

else

cuenta <= cuenta +'1';

end if;

end if;

end process;

q_out <=q_aux;

end arch_Comptador;

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi taquion,

    Change your line 46 to 52 to this and it should work, if there are no other problems: 

    Mapeig_Comptador: Comptador port map (
CLK_comp => CLOCK_50,
nReset => KEY(0),
q_out => cuentas  -- ms
);

    When you instantiate a component the component signal name is on the left side and the assigned signal on the right side.

    Best Regards,

    Mathias
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks Mathias it work great,

    Now I have solved all Errors but I have "Strange" warnings,

    Warning (10631): VHDL Process Statement warning at Ledsv2.vhd(57): inferring latch(es) for signal or variable "LEDR", which holds its previous value in one or more paths through the process

    What mean this, how can I control the LATCH of the ports or internal signals?

    Thanks,

    Guillermo
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    put ledr inside a clocked process. currently you don't give ledr a value for all combination of inputs, so you get a latch. synchronising it will remove this problem.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    thanks Tricky, but I have the same LATCH problems with the rest of signals,

    Warning (10631): VHDL Process Statement warning at Ledsv2.vhd(57): inferring latch(es) for signal or variable "nReset", which holds its previous value in one or more paths through the process

    Warning (10631): VHDL Process Statement warning at Ledsv2.vhd(57): inferring latch(es) for signal or variable "leds_r", which holds its previous value in one or more paths through the process

    Warning (10631): VHDL Process Statement warning at Ledsv2.vhd(57): inferring latch(es) for signal or variable "LEDR", which holds its previous value in one or more paths through the process

    Warning (10631): VHDL Process Statement warning at Ledsv2.vhd(57): inferring latch(es) for signal or variable "stat_act", which holds its previous value in one or more paths through the process

    Warning: LATCH primitive "stat_act" is permanently disabled

    Warning: LATCH primitive "leds_r[1]" is permanently disabled

    this exists from leds_r(0) to leds_r(17)

    Warning: LATCH primitive "LEDR[0]$latch" is permanently disabled

    Warning: Output pins are stuck at VCC or GND

    Warning (13410): Pin "LEDR[0]" is stuck at GND

    Warning (13410): Pin "LEDR[1]" is stuck at GND

    Warning (13410): Pin "LEDR[2]" is stuck at GND

    Warning (13410): Pin "LEDR[3]" is stuck at GND

    Warning (13410): Pin "LEDR[4]" is stuck at GND

    Warning (13410): Pin "LEDR[5]" is stuck at GND

    Warning (13410): Pin "LEDR[6]" is stuck at GND

    Warning (13410): Pin "LEDR[7]" is stuck at GND

    Warning (13410): Pin "LEDR[8]" is stuck at GND

    Warning (13410): Pin "LEDR[9]" is stuck at GND

    Warning (13410): Pin "LEDR[10]" is stuck at GND

    Warning (13410): Pin "LEDR[11]" is stuck at GND

    Warning (13410): Pin "LEDR[12]" is stuck at GND

    Warning (13410): Pin "LEDR[13]" is stuck at GND

    Warning (13410): Pin "LEDR[14]" is stuck at GND

    Warning (13410): Pin "LEDR[15]" is stuck at GND

    Warning (13410): Pin "LEDR[16]" is stuck at GND

    Warning (13410): Pin "LEDR[17]" is stuck at GND

    I think I don't understand how the latch works.

    I have a similiar code from a friend that works on a DE2-70, and there is no reference to any latch.

    What I'm missing?

    Thanks

    Guillermo
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    latched are registers without a clock. they are created when some combinations of inputs produce no output, so the logic has to remember the previous output. the way to fix it is to make sure the outputs have a value for every combination of inputs, ie you always have an else on an if statement or "when others " in a case statement. or you make each process a clocked process.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi Guillermo,

    I think your counter or 'Comptador' is in general ok. I assume that you running your design with a 50 MHz clock and the counter should increase its output ever 1 ms. In this case you should change your line: 

    if(cuenta= 50000) then

    to 

    if(cuenta= 49999) then

    or you count 50001 times instead of 50000.

    The source of your problems is that you don't clock your state machine in the 'Llums' process in LEDsv2.vhd.

    By the way, what are you intending to do with this state machine? I think you intending to increase 'led_r' every 250 ms right? But then you should compare to 249 or you wait 251 ms and set the reset back to '1' or the counter is always reseted.

    Best Regards

    Mathias
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You are getting lathces because you havent clocked your process inside Ledsv2.

    To remove latches, either

    1. Use the clock in the processes

    2. Make sure every if has an "else" branch and every case has a "when others => " branch.

    You are creating latches because for some combination of inputs the output holds its state, hence a latch. Here is an example: 

    
process
begin
  if input1 = '1' then
    output <= not input2;
  end if;
end process;

    Here, when input1 is '0', then output does not change, but holds the old value is was assigned the last time input1 was '1'. This is a latch. Your ledsv2 entity is full of code like this, hence you get latches.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi there,

    Thanks for the help, it work's!!!

    There was a problem with the clock and the nReset. It was always '0' and counter never start to count.

    Thanks,

    Guillermo