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Altera_Forum's avatar
Altera_Forum
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14 years ago

how to initialize the mega-rom with random values?

Hi, I tried to use the In System Memory Editor to set all the contents of the N identical sub-circuits' own ROM's content as random values. Since I need as more as such identical circuits as possible to do parallel computing, the only way I can came up with is use the "generate" function which looks like a "for" loop, with the number N sub-circuits I want to generate. Since the N sub-circuits have their own ROM, which need to be initialized to different random values. However if I use the megafunction to create the RAM, when initialize the mega-ROM with random values, after compiling, all the N ROMs have the same random values set, which is not what I want. So I used the In System Memory Editor to manually create random values for each ROM when the circuit is running. Since the in-system memory content editor can only support at most 255 system-level debug node, this method seems can not work to initialize all the ROMs with different random values.

Here I'd like to thank thepancake to help me point out this problem.

Can anyone be kind enough to give me some precious suggestions on how to do this? It is really appreciated for your help!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It should be possible to fill the ROM tables at compile time in VHDL code, using ieee.math_real.random with different seeds. Or externally generated *.hex/*.mif files.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The VHDL procedure is ieee.math_real.uniform(seed1, seed2, rand).

    Seed1 and seed2 are positive types, with rand being a random real value between 0 and 1. You can use this to scale an integer.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    It should be possible to fill the ROM tables at compile time in VHDL code, using ieee.math_real.random with different seeds. Or externally generated *.hex/*.mif files.

    --- Quote End ---

    Thank you so much for your kind reply. But the problem is that I can only use Verilog, and the how design is in Verilog. May I know if there is some similar code in Verilog that works similar? Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    The VHDL procedure is ieee.math_real.uniform(seed1, seed2, rand).

    Seed1 and seed2 are positive types, with rand being a random real value between 0 and 1. You can use this to scale an integer.

    --- Quote End ---

    Hi, thank you for the kind reply. Since I only learnt Verilog, is there any similar code in Verilog works in that way? Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    curious why you'd use a RAM for random numbers instead of logic?

    --- Quote End ---

    Hi, thanks for your reply. I need to use these random values to check if my circuit can converge to a stable state when given a initial state. Later, I will try to update the values in these RAMs to get better convergence, so I used RAMs. Do you have any suggestion on it? Thanks.