Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- It should be possible to fill the ROM tables at compile time in VHDL code, using ieee.math_real.random with different seeds. Or externally generated *.hex/*.mif files. --- Quote End --- Thank you so much for your kind reply. But the problem is that I can only use Verilog, and the how design is in Verilog. May I know if there is some similar code in Verilog that works similar? Thank you!