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Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- The VHDL procedure is ieee.math_real.uniform(seed1, seed2, rand). Seed1 and seed2 are positive types, with rand being a random real value between 0 and 1. You can use this to scale an integer. --- Quote End --- Hi, thank you for the kind reply. Since I only learnt Verilog, is there any similar code in Verilog works in that way? Thank you!