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CPR7's avatar
CPR7
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11 months ago

How to incorporate a VHDL file within Top level file in Quartus not using Platform Designer

Hello,

I am somewhat new to FPGA and new to using Quartus IDE. My question is that I could not incorporate

a file within the top level file that I created even after instantiating the .vhd file inside the top level

file. I would like to try to incorporate the file by not using Platform Designer. Is this possible?

Is there any reference that you could recommend that explains all about this.

Thanks in advance and regards.

14 Replies

  • FvM's avatar
    FvM
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    11 months ago

    Hi,
    it's not quite clear what you mean with "incorporate a file within the top level file"?


    Basically all VHDL files added to your project are compiled and all design entities found therein added to default library work unless explicitely assigned to a different library.


    Design entities are "incorporated" to your design by instantiating it in the design hierarchy, starting with the top level entity specified in Quartus project.

    The best reference is VHDL language reference IEEE Std. 1076 or a VHDL text book of your choice.

    Can you tell how far instantiation of design entities doesn't work for you?

    Regards
    Frank

    • CPR7's avatar
      CPR7
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      11 months ago

      Hello gentlemen,

      I apologize for the late reply about my problem. Being less experience using the Quartus II IDE my problem is how do I include or add a file to my top level design? I tried to use the option "Add/remove file to the project" but during the compilation process it gave an error with particulars attached. I also attached the top level design. Thank you in advance for your assistance.

      CPR7

      • FvM's avatar
        FvM
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        11 months ago
        Hi,
        according to compilation report, the design entity Hex7Seg isn't defined in any VHDL project file. Either the respective file hasn't been added to the project or it doesn't define the design entity correctly. We'd need to see the VHDL code to understand why.

        Regards
        Frank
    • CPR7's avatar
      CPR7
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      11 months ago

      Hi Kenny,

      I sent the .qar files but I don't know if they went through. Anyway I am sending again and I hope I sent the ones that you need.

    • CPR7's avatar
      CPR7
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      11 months ago

      Hi Kenny,

      I'll send them again. Hope it's correct. Thanks.

      • FvM's avatar
        FvM
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        11 months ago
        • Please try to append the .qar file to your post. Use button "Browse files to attach".
  • KennyT_altera's avatar
    KennyT_altera
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    10 months ago

    As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.