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CPR7's avatar
CPR7
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1 year ago

How to incorporate a VHDL file within Top level file in Quartus not using Platform Designer

Hello, I am somewhat new to FPGA and new to using Quartus IDE. My question is that I could not incorporate a file within the top level file that I created even after instantiating the .vhd file i...
Compilation
  • CPR7's avatar
    CPR7
    Icon for New Contributor rankNew Contributor
    11 months ago

    Hello gentlemen,

    I apologize for the late reply about my problem. Being less experience using the Quartus II IDE my problem is how do I include or add a file to my top level design? I tried to use the option "Add/remove file to the project" but during the compilation process it gave an error with particulars attached. I also attached the top level design. Thank you in advance for your assistance.

    CPR7

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      11 months ago
      Hi,
      according to compilation report, the design entity Hex7Seg isn't defined in any VHDL project file. Either the respective file hasn't been added to the project or it doesn't define the design entity correctly. We'd need to see the VHDL code to understand why.

      Regards
      Frank