How to handle the no connection ports in a module?

--- Quote Start ---

In some cases, I want to leave some input or output ports of a module no connection. E.g.:

ModuleA modulea_1 (.in1(),.in2(),……,.out1(),.out2(),……);

However, if I just program as above, to leave them blank, it will gives me warnings or even causes malfunction of the module.

So I wonder how to handle these no connection ports? Please explain separably, for input, and output.

If you can answer this same question but for VHDL programming, that will be great.

Thanks a lot!

--- Quote End ---

In vhdl you can map output to => open (or just ignore it)

For inputs you can't ignore it, you must drive it. If it is irrelevant then drive it with any constant value.

Note that your logic will be optimised accordingly.

--- Quote Start ---

Thanks very much, kaz. How about output in verilog?

--- Quote End ---

Try empty brackets(can't remember well):

out1(),

--- Quote Start ---

So you mean the warning is just warning. But leaving the output "blank" will not bring any negative effects on my design, right?

--- Quote End ---

If you don't want that output so be it. Your other outputs should not be affected unless you have some feedback chopped off from open output to an input.

The design itself will be optimised accordingly since any logic dedicated to drive unwanted output becomes redundant.