New Contributor
Super ContributorHi Gerhard,
Thank you for your detailed feedback and for sharing your experience across device families and Quartus versions.
Regarding the clock enable issue for RAM 2-port IP generation on Stratix 10 and Agilex 5: The behavior you observed—where enabling clock enables for read input/output registers is not supported in dual clock mode—is consistent with the hardware architecture differences between Arria 10 and newer device families (Stratix 10/Agilex 5). As noted in the Stratix® 10 Embedded Memory User Guide, independent clock enables are supported for certain modes, but the direct configuration you achieved on Arria 10 is not fully available on Stratix 10 and Agilex 5 due to these hardware changes.
The Quartus IP GUI restricts these settings to prevent unsupported configurations. While manual netlist modification may work for simulation and, in some cases, implementation, we strongly advise against this for production hardware, as it may not be reliably supported and could lead to unpredictable behavior.
For true dual-port, dual-clock RAMs requiring independent clock enables on both ports (as in your RX/TX FIFO application), the recommended approach is to use the emulated true dual-port (TDP) mode described in the Stratix 10/Agilex 5 Embedded Memory User Guides. This mode is designed to provide Arria 10-compatible behavior, though it may require some adjustments in your design flow.
We appreciate your efforts to test and validate in simulation and encourage further hardware testing if you proceed with manual modifications. However, for long-term robustness and supportability, we recommend adhering to Quartus-generated IP configurations and using emulated TDP mode where necessary.
Thanks
Best regards,
Kenny
Super ContributorHi Gerhard,
I found that for the dual-port configuration shown above, rden can be used instead of rdinclockenable. I see same behaviour for all combinations of input and output side enable.
Regards Frank
Super ContributorDo you mind to post another question to IP forum? I do know there are some setting within the Tranceiver Phy that can tune down some logic usage, but I am not sure about Ethernet.
Regarding FVM suggestion about using rden instead of rdinclockenable in the dual-port RAM configuration on Stratix 10 and Agilex 5: Due to hardware architecture differences in these newer device families, independent clock enables for the read input register (rdinclockenable) are not supported in true dual-port, dual-clock mode. However, you can use the rden (read enable) signal to control when read operations occur, effectively holding the output data steady when deasserted. While rden does not gate the address register in the same way as rdinclockenable, it serves as the supported method to manage read operations on these devices. If your design can accommodate this approach, adjusting your logic to utilize rden is recommended. Please note that if your application specifically requires clock gating of the address register, this functionality is not available in hardware on Stratix 10 and Agilex 5.
