Honored ContributorHi all,
I would like to know if there is some way to exclude some line of VHDL code from the simulation but not from the synthesis ! I know tha the opposite is possible using synthesis translate_off. I'm using Quartus 13.1 and Modelsim 10. Thank you
Honored ContributorFor code only visible to synthesis, you can use
-- ------------------------------------------------------------
-- Synthesis-only
-- ------------------------------------------------------------
--
-- Note: Quartus does not allow comments inside the read
-- comments as HDL block.
--
-- synthesis read_comments_as_HDL on
**** Synthesis VHDL in comments, but no VHDL comments ****
-- synthesis read_comments_as_HDL off
-- ------------------------------------------------------------
-- Simulation-only
-- ------------------------------------------------------------
--
-- altera translate_off
*** Simulation only code ***
-- altera translate_on
