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Altera_Forum's avatar
Altera_Forum
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12 years ago

how to exclude code from simulation?

Hi all, I would like to know if there is some way to exclude some line of VHDL code from the simulation but not from the synthesis ! I know tha the opposite is possible using synthesis translate...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

For code only visible to synthesis, you can use 


-- ------------------------------------------------------------
-- Synthesis-only
-- ------------------------------------------------------------
--
-- Note: Quartus does not allow comments inside the read
-- comments as HDL block.
--
-- synthesis read_comments_as_HDL on
**** Synthesis VHDL in comments, but no VHDL comments ****
-- synthesis read_comments_as_HDL off

For code only visible to simulation, you can use 


-- ------------------------------------------------------------
-- Simulation-only
-- ------------------------------------------------------------
--
-- altera translate_off
*** Simulation only code ***
-- altera translate_on

Cheers,

Dave