how to entrance & fanout internal logic cell

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Hi everybody.

I use quartusII 9.1-sp1 and i develop on cyclonne-III board with serial flash memory epcs4 with 16mhz crystal.

But on my development board, when i add some signals-probes for debugging, or other signals, misteriouly :confused: the board not run correctly :confused:

My dev board is buggy randomly after modify shematic and reprogramming memory of FPGA. Modif is very simple i add/sub not-cell and probes.

I try lcell, but it fell like.

What can i do ?

Please, what is entrance and fanout of general logics-cells Into cycIII fpga or Altera cpld ?

Excuse my bad English.

Thank you.

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Hi,

I assume you add some connection to signal, which you would like to see on FPGA pins.

Right ?

Kind regards

GPK

Thank you for your reply.

Is the unused pins can cause problems?

Other question : If i make a symbol an i name some signals, for example "clk1" , is that this signal is seen as a global signal, ie that the other symbols take "clk1" into account ?

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Thank you for your reply.

Is the unused pins can cause problems?

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Hi,

first of all you should look to the default setting of unused pins. You can found the setting looking under: Assignment -> Device -> Device and Pin options -> Unused pins

Maybe your setting is " Output driven ground". This must be change to "Tri-stated input".

When you add a new output did you assign the output to a certain pin ?

Kind regards

GPK

Hi

If i understand your reply : into the project settings > device and pin option > unused pin are setting to "as input tri stated with pull up resistor"

Thank.

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Hi

If i understand your reply : into the project settings > device and pin option > unused pin are setting to "as input tri stated with pull up resistor"

Thank.

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Hi,

yes, that should be the first step.

Kind regards

GPK